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Funded Research Projects
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Ashiq Sakib (PI), ‘CRII: SHF: Error Resilient Asynchronous Architecture for Ultra-Low Power Energy Harvesting IoT Applications,’ National Science Foundation (NSF), $175,000.
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Ashiq Sakib (PI), ‘STEP:A Design Framework for the Automated Synthesis, Advanced Optimization, and Verification of Quasi-Delay Insensitive (QDI) Asynchronous Circuits,’ Southern Illinois University Edwardsville, $16,000.
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Ashiq Sakib (PI), ‘Error Resilient Asynchronous Architectures for Ultra-Low Power Energy Harvesting IoT Devices’, Southeastern Center for Electrical Engineering Education (SCEEE), $55,000 [$27,500 (SCEEE) + $27,500 (FPU)]
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Ashiq Sakib (PI), ‘REU Extension: Error Resilient Asynchronous Architectures for Ultra-Low Power Energy Harvesting IoT Devices’, Southeastern Center for Electrical Engineering Education (SCEEE), $5,000.



Southeastern Center for Electrical Engineering Education (SCEEE)
Books/Book Chapters

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[IET'19] A. A. Sakib, S. Le, S. C. Smith, and S. K. Srinivasan, "Formal verification of NCL circuits," (Materials, Circuits & Devices, 2019), Asynchronous Circuit Applications, Chap. 15, pp. 309-338, DOI:10.1049/PBCS061E_ch15, IET Digital Library.
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[CRC'22] S. Chakrabarti, A. A. Sakib, et al., Editors. Interdisciplinary Research in Technology and Management, Proceedings of the International Conference on Interdisciplinary Research in Technology and Management (IRTM, 2022), 24-26th February 2022, Kolkata, India, 1st Edition, CRC Press, ISBN 9781032416267 (480 pages).

Peer-Reviewed Technical Articles
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[Journal: Electr.'25] Datta, Mithun, Dipayan Mazumder, Alexander C. Bodoh, and Ashiq A. Sakib. 2025. "DMR-SCL: A Design and Verification Framework for Redundancy-Based Resilient Asynchronous Sleep Convention Logic Circuits," Electronics 14, no. 5: 884. https://doi.org/10.3390/electronics14050884.
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[Journal: JLPEA'24] D. Mazumder, M. Datta, A. C. Bodoh, and A. A. Sakib, "A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits" in Journal of Low Power Electronics and Applications 14, no. 1: 5. https://doi.org/10.3390/jlpea14010005.
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[Journal: Access'23] D. Khodosevych, A. Bodoh, A. A. Sakib, and S. C. Smith, "Combining Relaxation with NCL_X for Enhanced Optimization of Asynchronous NULL Convention Logic Circuits," in in IEEE Access, 2023, doi: 10.1109/ACCESS.2023.3318132.
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[Journal: Access'22] D. Khodosevych and A. A. Sakib, "Evolution of QDI NULL Convention Logic-Based Asynchronous Paradigm: An Overview and Outlook," in in IEEE Access, 2022, doi: 10.1109/ACCESS.2022.3194028.
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[Journal: TVLSI'19] A. A. Sakib, S. C. Smith, and S. K. Srinivasan, "Formal Modeling and Verification of PCHB Asynchronous Circuits," in IEEE Transactions on Very-Large-Scale-Integration (VLSI) Systems, vol. 27, no. 12, pp. 2911-2924, Dec. 2019.
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[Conference: MWSCAS'25] H. Ziad and A. A. Sakib, "HALOC-AxA: An Area/Energy-Efficient Approximate Adder for Image Processing Applications," in IEEE MWSCAS, Michigan, US, 2025 (Accepted)
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[Conference: ISCAS'25] H. Ziad, A. Bodoh, and A. A. Sakib, "SR-NCL: an Area-/Energy Efficient Resilient NCL Architecture Based on Selective Redundancy," in IEEE ISCAS, London, UK, 2025 (Accepted)
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[Conference: ICECS'24] A. Bodoh and A. A. Sakib, "ASCEND: Advanced Synthesis, Circuit Exploration, and Design Optimization for NCL Circuits," 31st IEEE Int'l Conference on Electronics, Circuits and Systems (ICECS), Nancy, France, 2024, pp. 1-4.
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[Conference: NEWCAS'23] M. Datta, A. Bodoh, and A. A. Sakib, "Error Resilient Sleep Convention Logic Asynchronous Circuit Design," in 21st IEEE Interregional NEWCAS Conference (NEWCAS), Edinburgh, United Kingdom, 2023, pp. 1-5, doi: 10.1109/NEWCAS57931.2023.10198041.
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[Conference: UEMCON'22] A. Bodoh and A. A. Sakib, "Comparative Analysis of CNTFET and CMOS-Based NCL Asynchronous Circuits: A Study of Scaling Trends," in IEEE 13th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON), New York, NY, USA, 2022, pp. 407-412, doi: 10.1109/UEMCON54665.2022.9965723. [Best Presenter Award]
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[Conference: SBCCI'21] A. A. Sakib, "Soft Error Tolerant Quasi-Delay Insensitive Asynchronous Circuits: Advancements and Challenges," 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI), 2021, pp. 1-6, doi: 10.1109/SBCCI53441.2021.9530001.
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[Conference: ICECS'20] A. A. Sakib and S. C. Smith, "Implementation of Static NCL Threshold Gates Using Emerging CNTFET Technology," in 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Glasgow, UK, 2020, pp. 1-4, doi: 10.1109/ICECS49266.2020.9294823.
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[Conference: MWSCAS'20] A. A. Sakib, A. Akib, and S. C. Smith, “Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice,” in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA, 2020, pp. 37-40, doi: 10.1109/MWSCAS48704.2020.9184629.
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[Conference: ISCAS'19] M. Hossain, A. A. Sakib, S. K. Srinivasan, and S. C. Smith, "An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits," in IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5, doi: 10.1109/ISCAS.2019.8702098.
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[Conference: MWSCAS'18] A. A. Sakib, S. C. Smith, and S. K. Srinivasan, "An Equivalence Verification Methodology for Combinational Pre-Charge Half Buffer Asynchronous Circuits,” in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, ON, Canada, 2018, pp. 767-770, doi: 10.1109/MWSCAS.2018.8624068.​
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[Conference: MWSCAS'17] A. A. Sakib, S. C. Smith, and S. K. Srinivasan, "Formal Modeling and Verification for Pre-Charge Half Buffer Gates and Circuits," in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, USA, 2017, pp. 519-522, doi: 10.1109/MWSCAS.2017.8052974.

Dissertation
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[Dissertation] A. A. Sakib, “Formal Modeling and Verification Methodologies for Quasi-Delay Insensitive Asynchronous Circuits,” North Dakota State University, ProQuest Dissertations Publishing, 2019. 13904213.
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